Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
Cadence Janus NoC enables design teams to achieve better PPA faster and with lower risk, freeing up valuable engineering resources for SoC differentiation
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The Cadence Janus Network-on-Chip (NoC) efficiently manages simultaneous high-speed communications within and between silicon components with minimal latency. This enables customers to achieve their power, performance and area (PPA) targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. (Graphic: Business Wire)
“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said
The Cadence Janus NoC leverages Cadence’s legacy of trusted and time-proven
The Cadence Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects, which often don’t become apparent until physical implementation. Addressing the most pressing needs today, Cadence’s first-generation NoC provides a platform for future innovations, such as support for industry-standard memory and I/O coherence protocols. Current features and benefits include:
- Easy to use: Cadence’s powerful, state-of-the-art GUI enables easy NoC configuration ranging from small subsystems to full SoCs and future multi-chip systems.
- Accelerated time to market: PPA-optimized RTL enables SoC designers to achieve their bandwidth and latency goals. Packetized messages enable higher utilization of wires, reducing wire count and timing closure challenges.
- Lower risk: The NoC’s built-in power management, clock domain crossing and width matching reduce design complexity.
- Quick turnaround: Cadence’s extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements.
- Scalable architecture: Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system.
- Flexible: The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.
“We are pleased that Cadence is expanding its IP portfolio by investing in system-level solutions,” said
Availability and Related Resources
The Cadence Janus NoC will be available in
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For 10 years in a row,
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